Conventional network processors are often designed specifically for certain types of networking applications. For example, a given set of network processor hardware may be optimized for packet header processing and modification. Such an arrangement can advantageously provide a simple programming environment, resulting in less code being required to perform a given operation. However, it can also be unduly restrictive in terms of the range of packet processing operations that can be supported. For example, it may be difficult for a network processor with hardware optimized in the above-described manner to also accommodate enterprise network applications in which the network processor acts as a front end for one or more microprocessors performing protocol termination, transaction processing and firewall functions. Certain of the preliminary functions to be performed by the network processor in supporting enterprise network applications of this type may result in inefficient packet flows, and associated performance degradations, when conventional architectures are used.
A number of recent advances in network processors have provided improved flexibility and enhanced performance relative to prior conventional approaches. Examples of such techniques are described in U.S. Patent Application Publication Nos. 2003/0118020, entitled “Method and Apparatus for Classification of Packet Data Prior to Storage in Processor Buffer Memory,” 2003/0118023, entitled “Processor with Packet Processing Order Maintenance Based on Packet Flow Identifiers,” and 2003/0120790, entitled “Processor with Multiple-Pass Non-Sequential Packet Classification Feature,” all of which are commonly assigned herewith and incorporated by reference herein.
Notwithstanding the considerable advances provided by the techniques outlined in the above-cited U.S. patent applications, a need remains for further improvements in network processor architectures, particularly with regard to providing support for enterprise network applications as a front end for one or more microprocessors.